Priority is claimed from Republic of Korean Patent Application No. 99-63895 filed Dec. 28, 1999, which is incorporated in its entirety by reference.
1. Field of the Invention
The invention relates generally to a method of improving an electrostatic discharge (hereinafter called xe2x80x9cESDxe2x80x9d) characteristic in a flash memory device. More particularly, the present invention relates to, a method of improving an ESD characteristic in a flash memory device which can prevent generation of leak current, that is caused when charges generated upon testing of the ESD are introduced into an internal circuit.
2. Description of the Prior Art
In general, the test method of measuring an ESD level involves a Human Body Model (xe2x80x9cHBMxe2x80x9d) of a high voltage/low current model and a Machine Model of a low voltage/high current model. Upon measurement of the ESD level, as electric field paths can be formed from the input pin toward the power supply terminal Vcc and from the input pin toward the ground terminal Vss, both the Vcc basis and the Vss basis must be tested. Also, as it may vary depending on a field direction, when it is the Vcc basis (or Vss basis), the Vcc is grounded and the positive voltage and the negative voltage are applied to the corresponding pins, respectively, three times.
Then, during the Human Body Model Vcc negative zapping, a current fail (Isb fail) is generated by the leak current I1kg in the data output (DQ) pin. At this time, the cause of generation of the current fail (Isb fail) will be below explained by reference to FIGS. 1 and 2.
FIGS. 1 and 2 are diagrams for explaining generation of fail in an internal circuit upon a conventional testing of an electrostatic discharge.
In a standby state, a power supply voltage is directly applied to the NMOS drain junction of an internal circuit 15 and a SDA input buffer through a Vcc pad 12. Also, a neighboring NMOS source junction is connected to the ground terminal via a Vss pad 13. In this state, if charges are discharged through the Vcc supply line by the ESD stress, the charges are introduced into the internal circuit 15, thus connecting the Vcc and the Vss on the border of a field oxide film in most of the internal circuit. Then, damage is generated at a weaken portion in the circuit and current fail 15, A is therefore generated.
That is, conventionally, there is a problem that the ESD characteristic is degraded such as generation of current fail, etc. because the Vcc line and the Vss line are neighboring to each other by a distance D (2.7 xcexcm) on the border of the field oxide film at the connection of the internal circuit and the SDA input buffer.
It is therefore an object of the present invention to provide a method of improving an electrostatic discharge characteristic in a flash memory device capable of preventing current fail in the internal circuit, by not neighboring a Vss line and a Vcc line to each other in the connection of the internal circuit and a SDA input buffer.
In order to accomplish the above object, a method of improving an electrostatic discharge characteristic in a flash memory device according to the present invention is characterized in that it comprises the step of connecting a drain junction power supply terminal and a ground terminal line, in the connection of an internal circuit and a SDA input buffer in a flash memory device, to connection terminals spaced apart to each other.